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preliminary 3.3v 4k/8k x 18 synchronous dual-port static ram cy7c09349v CY7C09359V cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 october 14, 1999 1 features ? true dual-ported memory cells which allow simulta- neous access of the same memory location two flow-through/pipelined devices ? 4k x 18 organization (cy7c09349v) ? 8k x 18 organization (CY7C09359V) three modes ? flow-through ?pipelined ?burst pipelined output mode on both ports allows fast 83-mhz operation 0.35-micron cmos for optimum speed/power high-speed clock to data access 7.5 [1, 2] /9/12 ns (max.) 3.3v low operating power ? active = 135 ma (typical) ? standby = 10 a (typical) fully synchronous interface for easier operation burst counters increment addresses internally ? shorten cycle times ? minimize bus noise ? supported in flow-through and pipelined modes dual chip enables for easy depth expansion upper and lower byte controls for bus matching automatic power-down commercial and industrial temperature ranges available in 100-pin tqfp notes: 1. call for availability 2. see page 6 for load conditions. 3. a 0 ?a 11 for 4k; a 0 ?a 12 for 8k devices. v logic block diagram r/w l 1 0 0/1 ce 0l ce 1l lb l oe l ub l 1b 0/1 0b 1a 0a ba ft /pipe l i/o 9l ?i/o 17l i/o 0l ?i/o 8l i/o control counter/ address register decode a 0l ?a 11/12l clk l ads l cnten l cntrst l true dual-ported ram array r/w r 1 0 0/1 ce 0r ce 1r lb r oe r ub r 1b 0/1 0b 1a 0a b a ft /pipe r i/o control counter/ address register decode 12/13 9 9 i/o 9r ?i/o 17r i/o 0r ?i/o 8r a 0r ?a 11/12r clk r ads r cnten r cntrst r 12/13 9 9 [3] [3] for the most recent information, visit the cypress web site at www.cypress.com
cy7c09349v CY7C09359V 2 preliminary functional description the cy7c09349v and CY7C09359V are high-speed 3.3v synchronous cmos 4k and 8k x 18 dual-port static rams. two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. [4] reg- isters on control, address, and data lines allow for minimal set- up and hold times. in pipelined output mode, data is registered for decreased cycle time. clock to data valid t cd2 = 7.5 ns [1] (pipelined). flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. in flow-through mode data will be available t cd1 = 18 ns after the address is clocked into the device. pipelined output or flow- through mode is selected via the ft /pipe pin. each port contains a burst counter on the input address regis- ter. the internal write pulse width is independent of the low- to-high transition of the clock signal. the internal write pulse is self-timed to allow the shortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle will power down the internal circuitry to reduce the static power consump- tion. the use of multiple chip enables allows easier banking of multiple chips for depth expansion configurations. in the pipelined mode, one cycle is required with ce 0 low and ce 1 high to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and ut ilize the internal address generated by the internal counter for fast interleaved memory applications. a port ? s burst counter is loaded with the port ? s address strobe (ads ). when the port ? s count enable (cnten ) is asserted, the address counter will increment on each low-to-high transition of that port ? s clock signal. this will read/write one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array and will loop back to the start. counter reset (cntrst ) is used to reset the burst counter. all parts are available in 100-pin thin quad plastic flatpack (tqfp) packages. note: 4. when simultaneously writing to the same location, final value cannot be guaranteed.
cy7c09349v CY7C09359V 3 preliminary pin configuration note: 5. this pin is nc for cy7c09349v. selection guide cy7c09349v CY7C09359V -7 [1, 2] cy7c09349v CY7C09359V -9 cy7c09349v CY7C09359V -12 f max2 (mhz) (pipelined) 83 67 50 max access time (ns) (clock to data, pipelined) 7.5 9 12 typical operating current i cc (ma) 155 135 115 typical standby current for i sb1 (ma) (both ports ttl level) 25 20 20 typical standby current for i sb3 ( a) (both ports cmos level) 10 a10 a10 a shaded areas contain advance information. 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a8r a9r a10r a11r a12r nc ce0r nc ubr cntrstr r/wr ft /piper i/o17r lbr nc gnd oer gnd i/o16r i/o15r i/o14r i/o13r i/o12r i/o11r ce1r 58 57 56 55 54 53 52 51 a9l a10l a11l a12l nc nc ce1l lbl ce0l r/wl oel i/o17l i/o16l ubl nc vcc ft /pipel gnd i/o15l i/o14l i/o13l 1/012l i/o11l i/o10l cntrstl 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l clkl a1l cntenl gnd gnd cntenr a0r a0l a2l adsr clkr a1r a2r a3r a4r a5r a6r a7r adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 i/10r i/o9r i/o8r i/o7r vcc i/o6r i/01r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 100-pin tqfp (top view) [note 5] [note 5] cy7c09349v (4k x 18) CY7C09359V (8k x 18)
cy7c09349v CY7C09359V 4 preliminary maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +4.6v dc voltage applied to outputs in high z state ........................... ? 0.5v to v cc +0.5v dc input voltage ...................................... ? 0.5v to v cc +0.5v output current into outputs (low) ............................. 20 ma static discharge voltage ........................................... >2001v latch-up current..................................................... >200 ma pin definitions left port right port description a 0l ? a 12l a 0r ? a 12r address inputs (a 0 ? a 11 for 4k, a 0 ? a 12 for 8k devices). ads l ads r address strobe input. used as an address qualifier. this signal should be asserted low during normal read or write transactions. asserting this signal low also loads the burst address counter with data present on the i/o pins. ce 0l ,ce 1l ce 0r ,ce 1r chip enable input. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). clk l clk r clock signal. this input can be free running or strobed. maximum clock input rate is f max . cnten l cnten r counter enable input. asserting this signal low increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if ads or cntrst are asserted low. cntrst l cntrst r counter reset input. asserting this signal low resets the burst address counter of its respec- tive port to zero. cntrst is not disabled by asserting ads or cnten . i/o 0l ? i/o 17l i/o 0r ? i/o 17r data bus input/output (i/o 0 ? i/o 15 for x16 devices). lb l lb r lower byte select input. asserting this signal low enables read and write operations to the lower byte (i/o 0 ? i/o 8 for x18, i/o 0 ? i/o 7 for x16) of the memory array. for read operations both the lb and oe signals must be asserted to drive output data on the lower byte of the data pins. ub l ub r upper byte select input. same function as lb , but to the upper byte (i/o 8/9l ? i/o 15/17l ). oe l oe r output enable input. this signal must be asserted low to enable the i/o data pins during read operations. r/w l r/w r read/write enable input. this signal is asserted low to write to the dual port memory array. for read operations, assert this pin high. ft /pipe l ft /pipe r flow-through/pipelined select input. for flow-through mode operation, assert this pin low. for pipelined mode operation, assert this pin high. gnd ground input. nc no connect. v cc power input. operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 300 mv industrial ? 40 c to +85 c 3.3v 300 mv shaded areas contain advance information.
cy7c09349v CY7C09359V 5 preliminary note: 6. ce l and ce r are internal signals. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). electrical characteristics over the operating range parameter description cy7c09349v CY7C09359V unit -7 [1, 2] -9 -12 min. typ. max. min. typ. max. min. typ. max. v oh output high voltage (v cc = min., i oh = ? 4.0 ma) 2.4 2.4 2.4 v v ol output low voltage (v cc = min., i oh = +4.0 ma) 0.4 0.4 0.4 v v ih input high voltage 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 v i oz output leakage current ? 10 10 ? 10 10 ? 10 10 a i cc operating current (v cc = max., i out = 0 ma) outputs disabled com ? l. 155 275 135 230 115 180 ma indust. 185 300 155 250 ma i sb1 standby current (both ports ttl level) [6] ce l & ce r v ih , f =f max com ? l. 25 85 20 75 20 70 ma indust. 35 85 30 80 ma i sb2 standby current (one port ttl level) [6] ce l | ce r v ih , f =f max com ? l. 105 165 95 155 85 140 ma indust. 106 165 95 150 ma i sb3 standby current (both ports cmos level) [6] ce l & ce r v cc ? 0.2v, f = 0 com ? l. 10 250 10 250 10 250 a indust. 10 250 10 250 a i sb4 standby current (one port cmos level) [6] ce l | ce r v ih , f = f max com ? l. 95 125 85 115 75 100 ma indust. 95 125 85 110 ma shaded areas contain advance information. capacitance parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 10 pf c out output capacitance 10 pf
cy7c09349v CY7C09359V 6 preliminary ac test loads (applicable to -7 only) [7] note: 7. test conditions: c = 10 pf. ac test loads (a) normal load (load 1) r1 = 590 ? 3.3v output r2 = 435 ? c= 30 pf v th =1.4v output c= 30 pf (b) th venin equivalent (load 1) (c) three-state delay (load 2) r1 = 590 ? r2 = 435 ? 3.3v output c= 5pf r th =250 ? (used for t cklz , t olz , & t ohz including scope and jig) v th =1.4v output c (a) load 1 (-7 only) r = 50 ? z 0 = 50 ? 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses 0.00 0.1 0 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1 0 1 5 20 25 30 35 (b) load derating curve capacitance (pf) ? (ns) for all -7 access times
cy7c09349v CY7C09359V 7 preliminary switching characteristics over the operating range parameter description cy7c09349v CY7C09359V unit -7 [1, 2] -9 -12 min. max. min. max. min. max. f max1 f max flow-through 45 40 33 mhz f max2 f max pipelined 83 67 50 mhz t cyc1 clock cycle time - flow-through 22 25 30 ns t cyc2 clock cycle time - pipelined 12 15 20 ns t ch1 clock high time - flow-through 7.5 12 12 ns t cl1 clock low time - flow-through 7.5 12 12 ns t ch2 clock high time - pipelined 5 68ns t cl2 clock low time - pipelined 5 68ns t r clock rise time 333ns t f clock fall time 333ns t sa address set-up time 4 44ns t ha address hold time 0 11ns t sc chip enable set-up time 4 44ns t hc chip enable hold time 0 11ns t sw r/w set-up time 4 44ns t hw r/w hold time 0 11ns t sd input data set-up time 4 44ns t hd input data hold time 0 11ns t sad ads set-up time 4 44ns t had ads hold time 0 11ns t scn cnten set-up time 4 44ns t hcn cnten hold time 0 11ns t srst cntrst set-up time 4 44ns t hrst cntrst hold time 0 11ns t oe output enable to data valid 91012ns t olz oe to low z 2 22ns t ohz oe to high z 1 71717ns t cd1 clock to data valid - flow-through 18 20 25 ns t cd2 clock to data valid - pipelined 7.5 9 12 ns t dc data output hold after clock high 2 22ns t ckhz clock high to output high z 2 92929ns t cklz clock high to output low z 2 22ns port to port delays t cwdd write port clock high to read data delay 35 40 40 ns t ccs clock to clock set-up time 10 15 15 ns shaded areas contain advance information.
cy7c09349v CY7C09359V 8 preliminary switching waveforms read cycle for flow-through output (ft /pipe = v il ) [8, 9, 10, 11] read cycle for pipelined operation (ft /pipe = v ih ) [8, 9, 10, 11] notes: 8. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 9. ads = v il , cnten and cntrst = v ih . 10. the output is disabled (high-impedance state) by ce 0 =v ih or ce 1 = v il following the next rising edge of the clock. 11. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce 0 ce 1 r/w address data out oe t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce 0 ce 1 r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency
cy7c09349v CY7C09359V 9 preliminary bank select pipelined read [12, 13] left port write to flow-through right port read [14, 15, 16, 17] notes: 12. in this depth expansion example, b1 represents bank #1 and b2 is bank #2. each bank consists of one cypress dual-port device from this data sheet. address (b1) = address (b2) . 13. ub , lb , oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/w , cnten , and cntrst = v ih . 14. the same waveforms apply for a right port write to flow-through left port read. 15. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . 16. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 17. it t ccs maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs >maximum specified, then data is not valid until t ccs + t cd1 . t cwdd does not apply in this case. switching waveforms (continued) d 3 d 1 d 0 d 2 a 0 a 1 a 2 a 3 a 4 a 5 d 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce 0(b1) data out(b2) data out(b1) address (b2) ce 0(b2) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/w l address l data inl address r data outr clk r r/w r
cy7c09349v CY7C09359V 10 preliminary pipelined read-to-write-to-read (oe = v il ) [11, 18, 19, 20] pipelined read-to-write-to-read (oe controlled) [11, 18, 19, 20] notes: 18. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 19. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 20. during ? no operation, ? data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce 0 ce 1 r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3 t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce 0 ce 1 r/w address data out data in oe
cy7c09349v CY7C09359V 11 preliminary flow-through read-to-write-to-read (oe = v il ) [9, 11, 19, 20] flow-through read-to-write-to-read (oe controlled) [9, 11, 18, 19, 20] switching waveforms (continued) t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce 0 ce 1 address r/w data in data out q n t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce 0 ce 1 address r/w data in data out oe
cy7c09349v CY7C09359V 12 preliminary pipelined read with address counter advance [21] flow-through read with address counter advance [21] note: 21. ce 0 and oe = v il ; ce 1 , r/w and cntrst = v ih . switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x-1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn a n t sad t had t scn t hcn t cd1 clk address ads cnten q x q n q n+1 t dc counter hold read with counter read external address read with counter q n+3 q n+2 data out
cy7c09349v CY7C09359V 13 preliminary write with address counter advance (flow-through or pipelined outputs) [22, 23] notes: 22. ce 0 , ub , lb , and r/w = v il ; ce 1 and cntrst = v ih . 23. the ? internal address ? is equal to the ? external address ? when ads = v il and equals the counter output when ads = v ih . switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cnten ads data in address t sa t ha
cy7c09349v CY7C09359V 14 preliminary counter reset (pipelined outputs) [11, 18, 24, 25] notes: 24. ce 0 , ub , and lb = v il ; ce 1 = v ih . 25. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 q n d 0 a x 01a n a n+1 t sad t had t scn t hcn t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n
cy7c09349v CY7C09359V 15 preliminary notes: 26. ? x ? = ? don ? t care, ? ? h ? = v ih , ? l ? = v il . 27. ads , cnten , cntrst = ? don ? t care. ? 28. oe is an asynchronous input signal. 29. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 30. ce 0 and oe = v il ; ce 1 and r/w = v ih . 31. data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 32. counter operation is independent of ce 0 and ce 1 . read/write and enable operation [26, 27, 28] inputs outputs oe clk ce 0 ce 1 r/w i/o 0 ? i/o 17 operation x h x x high-z deselected [29] x x l x high-z deselected [29] x l h l d in write l l h h d out read [29] h x l h x high-z outputs disabled address counter control operation [26, 30, 31, 32] address previous address clk ads cnten cntrst i/o mode operation x x x x l d out(0) reset counter reset to address 0 a n x l x h d out(n) load address load into counter x a n h h h d out(n) hold external address blocked ? counter disabled x a n h l h d out(n+1) increment counter enabled ? internal address generation
cy7c09349v CY7C09359V 16 preliminary ordering information document #: 38 ? 00676 ? c 4k x18 3.3v synchronous dual-port sram speed (ns) ordering code package name package type operating range 7.5 [1, 2] cy7c09349v ? 7ac a100 100-pin thin quad flat pack commercial 9 cy7c09349v ? 9ac a100 100-pin thin quad flat pack commercial cy7c09349v ? 9ai a100 100-pin thin quad flat pack industrial 12 cy7c09349v ? 12ac a100 100-pin thin quad flat pack commercial cy7c09349v ? 12ai a100 100-pin thin quad flat pack industrial 8k x18 3.3v synchronous dual-port sram speed (ns) ordering code package name package type operating range 7.5 [1, 2] CY7C09359V ? 7ac a100 100-pin thin quad flat pack commercial 9 CY7C09359V ? 9ac a100 100-pin thin quad flat pack commercial CY7C09359V ? 9ai a100 100-pin thin quad flat pack industrial 12 CY7C09359V ? 12ac a100 100-pin thin quad flat pack commercial CY7C09359V ? 12ai a100 100-pin thin quad flat pack industrial shaded areas contain advance information. package diagram 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-a

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